1. Field of the Invention
The present invention relates to an adhesive composition for semiconductor chip lamination particularly suitable for “chip stacking”, the adhesive composition being used in a step of bonding a substrate and a chip or bonding chips and in a step of bonding a substrate and a chip or bonding chips using semiconductor chips obtained by dicing a silicon wafer or the like and then picking up the diced silicon wafer. The present invention also relates to a semiconductor chip laminate that uses the adhesive composition for semiconductor chip lamination.
2. Description of the Related Art
Semiconductor wafers made of silicon, gallium arsenide, and the like are manufactured with a large diameter. Such a wafer is cut (diced) into small element pieces (semiconductor chips) and then transferred to a bonding step performed next. After dicing, cleaning, drying, expanding, and picking-up steps are performed while the semiconductor wafer is attached to an adhesive sheet in advance, it is transferred to a ponding step performed next.
In the bonding step, an adhesive sheet is used to bond a substrate and a chip, bond chips, or the like. To simplify the process of the picking-up step and the bonding step among the steps described above, there are proposed various adhesive sheets for dicing and die bonding that have both a wafer fixing function and a die bonding function (e.g., refer to Japanese Unexamined Patent Application Publications No. 2-32181, No. 8-239636, No. 10-8001, and No. 2000-17246).
With such adhesive sheets, “direct die bonding” is achieved and a step of applying a liquid adhesive for die bonding can be omitted.
On the other hand, there is “a laminated semiconductor device” in which semiconductor chips are three-dimensionally laminated to achieve the speed-up and downsizing of semiconductor devices.
There have been proposed a device in which a small chip is laminated on a large chip (e.g., Japanese Unexamined Patent Application Publication No. 7-38053), a device in which chips each having a step in the periphery thereof are laminated (e.g., Japanese Unexamined Patent Application Publication No. 6-244360), and a device in which two chips are bonded to each other so as to face in opposite directions, and one of the chips is directly bonded to a substrate and the other of the chips is bonded to a substrate through a bonding wire (e.g., Japanese Unexamined Patent Application Publication No. 7-273275).
For the adhesion of the laminated chips of the laminated semiconductor devices, a dicing/die bonding sheet is more widely used than a liquid die-attaching adhesive in consideration of the quality (variation in height of chip lamination and chip tilt) and productivity of semiconductor devices.
An adhesive of the dicing/die bonding sheet includes an acrylic polymer and an epoxy thermosetting resin as a component that develops an adhesive force, and often further includes a thermal curing agent and a thermal curing accelerator for the epoxy resin.
An imidazole compound is widely used as the thermal curing accelerator in terms of the temporal stability and productivity of the sheet.